`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:15:57 04/13/2009 
// Design Name: 
// Module Name:    piperegEXMEM 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module piperegEXMEM(in1, in2, in3,in4,in5,in6,in7,in8, clk, out1,out2,out3,out4,out5,out6,out7,out8);
    input [31:0] in1,in3;
    input in2,in4,clk, in5,in6,in7,in8;
    output [31:0] out1,out3;
	 output out2,out4,out5,out6,out7,out8;
	 	 
	 reg [31:0] out1,out3;
	 reg out2,out4,out5,out6,out7,out8;
	 	 
	 always @ (posedge clk)
	 begin
	 out1 = in1;
	 out2 = in2;
	 out3 = in3;
	 out4 = in4;
	 out5 = in5;
	 out6 = in6;
	 out7 = in7;
	 out8 = in8;
	 end
endmodule
